The present invention relates generally to semiconductor device manufacturing and, more particularly, to forming silicon-on-insulator (SOI) substrates having selected strained and relaxed silicon device regions.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET or MOS), in which a gate structure is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-type and p-type transistors (NFET and PFET) are used to fabricate logic and other circuitry.
The source and drain regions of an FET are typically formed by adding dopants to targeted regions of a semiconductor body on either side of the channel. A gate structure is formed above the channel, which includes a gate dielectric located over the channel and a gate conductor above the gate dielectric. The gate dielectric is an insulator material, which prevents large leakage currents from flowing into the channel when a voltage is applied to the gate conductor, while allowing the applied gate voltage to set up a transverse electric field in the channel region in a controllable manner. Conventional MOS transistors typically include a gate dielectric formed by depositing or by growing silicon dioxide (SiO2) or silicon oxynitride (SiON) over a silicon wafer surface, with doped polysilicon formed over the SiO2 to act as the gate conductor.
The escalating demands for high density and performance associated with ultra large scale integrated (ULSI) circuit devices have required certain design features, such as shrinking gate lengths, high reliability and increased manufacturing throughput. The continued reduction of design features has challenged the limitations of conventional fabrication techniques. One of the more important indicators of potential device performance is the carrier mobility. There is a significant challenge with respect to keeping carrier mobility high in devices of deeply submicron generations.
The gain of an FET, usually defined by the transconductance (gm), is proportional to the mobility (μ) of the majority carrier in the transistor channel. The current carrying capability, and hence the performance of an FET is proportional to the mobility of the majority carrier in the channel. The mobility of holes, which are the majority carriers in a PFET, and the mobility of electrons, which are the majority carriers in an NFET transistor, may be enhanced by applying an appropriate stress to the channel. Existing stress engineering methods greatly enhance circuit performance by increasing device drive current without increasing device size and device capacitance. For example, a tensile stress liner applied to an NFET transistor induces a longitudinal stress in the channel and enhances the electron mobility, while a compressive stress liner applied to a PFET transistor induces a compressive stress in the channel and enhances the hole mobility.